The present invention relates to a structure of a memory macro of a semiconductor chip on a one chip in which a memory storing data and a logic performing a specific operation on the data are integrated and a designing method for the memory macro.
FIG. 40 shows a layout of a memory integrated with a logic on a chip.
The chip 10 is occupied by a logic section 11, a memory section (hereinafter referred to as memory macro) 12 and an input/output section (hereinafter referred to as I/O section) 13. The memory macro 12 is formed in such a manner that after a functional block (IP: Intellectual Property) or megacell having a function as a memory is designed, the functional block or the megacell is arranged on the chip as it is.
In the chip 10, at least one memory macro 12 is arranged. As shown in FIG. 41, the chip 10 may be provided with functional blocks (or megacells) 14a, 14b each having a specified function such as PPL circuit or the like in addition to the memory macro 12. A logic section 11 in which a circuit for executing a specific operation is formed occupies the region other than regions which the memory macro 12 and the functional blocks 14a, 14b occupy respectively.
The logic section 11 is designed by use of a designing method for a gate array or a standard cell.
In the case where the memory macro 12 is constructed from SRAMs (static random access memory), the memory macro 12 is designed by an automatically designing method which automatically determines a layout of a memory cell array in a matrix forming a predetermined number of rows and a predetermined number of columns by use of CAD processing.
When the memory macro 12 is constituted of a DRAM (dynamic random access memory) having a storage capacity of 1 Mbits or more, the automatically designing method cannot be applied in a design of the memory macro 12 since an operational margin of a DRAM is strongly dependent on parasitic capacitance of a bit line and a bit line
Therefore, when the memory macro 12 is constituted of a DRAM having a storage capacity of 1 Mbits or more, a designing method has conventionally been accepted as a general way that a memory macro as the minimal unit of storage capacity, that is a so-called a sub memory macro, is manually designed by a designer in advance and a necessary number of sub memory macros are combined according to a specification of a logic in memory integrated circuit: that is the number of rows, the number of columns, the number of inputs and outputs (the number of I/Os), a storage capacity etc. According to this designing method, since only a combination of sub memory macros makes it possible to form a memory macro, the memory macro can be designed in a short period (TAT: a turnaround time). Each sub memory macro can independently be operated, for example, one sub memory macro can be sold on the market as a usual DRAM.
FIG. 42 shows an example of a floor plan for a conventional memory macro.
The memory macro 12 comprises, for example, four sub memory macro 15a to 15d each functioning as one DRAM having a storage capacity of 2 Mbits. Since each sub memory macro functions as a DRAM having a storage capacity of 2 Mbits, the memory macro 12 is a DRAM having a storage capacity of 8 (2.times.L) Mbits (L indicates the number of sub memory macros and herein the case of L=4 is taken up as an example).
FIG. 43 shows a block diagram of the sub memory macro 15a shown in FIG. 42.
The sub memory macro 15a includes all the circuits necessary for a DRAM to operate in a perfect manner as an independent one. That is, the sub memory macro 15a comprises: a memory cell array 20, a sense amplifier 21, a row decoder 22, a column decoder 23, an input/output data buffer 24, a row address buffer 25; a column address buffer 26, a row control circuit 27, a column control circuit 28, a substrate potential generating circuit 29, a word line potential generating circuit 30, a bit line potential generating circuit 31, a sense amplifier power source driver reference potential generating circuit 32, a peripheral circuit power source potential generating circuit 33 and a sense amplifier power source driver transistor 34.
As an example, an external power source VEXT is about 3.3V, a substrate potential VBB is about -1V, a word line potential VPP is about 4.3V, a bit line potential VBL is about 1.3V, a sense amplifier power source potential VAA is about 2.5V and a peripheral circuit power source potential VINT is about 2.8V. Sub memory macros 15b to 15d are constructed in the same structure as this.
When a plurality of sub memory macros 15a shown in FIG. 43 are combined into one memory macro, since each of the sub memory macros 15a to 15d comprises: a row address buffer 25, a column address buffer 26, a row control circuit 27, a column control circuit 28, a substrate potential generating circuit 29, a word line potential generating circuit 30, a bit line potential generating circuit 31, a sense amplifier power source driver reference potential generating circuit 32, a peripheral circuit power source potential generating circuit 33 and a sense amplifier power source driver transistor 34, the memory macro has to be provided with the above mentioned circuits included in the plurality of sub memory macros 15a.
That is, since the more the number of sub memory macros 15a, the more the number of each of the above mentioned circuits, increase in area of a memory macro is resulted. However, there is no need for providing all the circuits included the sub memory macros 15a to 15d, wherein each sub memory macro 15a comprises a row address buffer 25, a column address buffer 26, a row control circuit 27, a column control circuit 28, a substrate potential generating circuit 29, a word line potential generating circuit 30, a bit line potential generating circuit 31, a sense amplifier power source driver reference potential generating circuit 32, a peripheral circuit power source potential generating circuit 33 and a sense amplifier power source driver transistor 34, but only one circuit system is sufficiently provided in one memory macro 12.
As a designing method to solve this fault, the following method has been proposed.
A designing method of FIG. 44 is disclosed in Jpn. Pat. Appln. SHUTSUGAN Publication No. 7-13738 (filed on Jan. 31, 1995).
This method provides a memory macro 12 comprising a plurality of, for example 4 sub memory macros 16a to 16d, one control section (control macro) 17 and a interconnection section 18 in order to realize a desired storage capacity. According to the method, unnecessary increase in chip area of the memory macro can be prevented from occurring since there is a control macro 17 shared by a plurality of sub memory macro 16a to 16d.
Another designing method is a method disclosed in T. Watanabe et al., "A Modular Architecture for a 6.4 Gbytes, 8 Mb DRAM-Integrated Media Chip," IEEE J. Solid-State Circuits, vol. 32, pp. 635-641, May 1997.
This designing method provides a memory macro 41 comprising a plurality of a memory block (bank) 42, a predetermined potential generating circuit 43, a sense amplifier 44 and a data input/output section 45. On the chip 40, a control section (control logic) 46 for the memory macro 41 and a logic section (operational circuit) 47 are arranged in addition to the memory macro 41. According to the method, sets each consisting of a predetermined potential generating circuit 43, a sense amplifier 44, a data input/output section 45 and a control section 46 are not respectively provided to a plurality of memory blocks (bank) 42 but one set is provided for common use, therefore unnecessary increase in chip area of the memory macro to be caused by increase in the number of memory blocks 42 is prevented form occurring.
According to designing methods of FIGS. 44 and 45, since a memory macro having a desired storage capacity can be achieved only if the number of sub memory macros or memory blocks is adjusted, whereby designing period for a memory integrated with a logic can be shortened. Since neither sub memory macros nor memory blocks respectively contain circuits each of which can commonly be used, the memory macro is prevented from being enlarged in area more than necessary when the number of sub memory macros or memory blocks is increased.
However, if the number of sub memory macros or memory blocks is changed according to a different specification (the number of rows, the number of columns, the number of I/O, storage capacity etc.) of a memory integrated with a logic, for example, whereby the number of address signals which are required for memory operation is also changed and predetermined circuits such as an address buffer, a address decoder etc. have to be redesigned accordingly.
A specification of a memory macro with a storage capacity less than one Mbit memory array, which is essentially an enlargement unit, for example 64 Kb and 32 Kb has conventionally been obtained by design change of one Mb memory array. However, a design change of an memory array itself is accompanied with a basic change thereof and this change can not be automatically performed in CAD processing and thereby it is time-consuming. The number of I/Os of an input/output data buffer is also required to be changed according to the number of DQ line pairs of a memory array which is changed in design.